Bachelor

Oct 1, 1997 - Jun 24, 2001

computer engineering technology

Master

Aug 13, 2025 - Jan 15, 2012

computer engineering technology

Design and implementation of reduced number of switches for new multilevel inverter topology without zero-level state

Mar 1, 2022

Journal International Journal of Power Electronics and Drive Systems(IJPEDS)

publisher International Journal of Power Electronics and Drive Systems(IJPEDS)

DOI http://doi.org/10.11591/ijpeds.v13.i1.pp401-410

Volume Vol. 13, No. 1

Currently, multilevel inverter (MLI) has been chosen over conventional inverter because of less harmonic distortions and higher output voltage levels. In this paper, 15-level inverter with reduced number of power switching devices is designed. Different output voltage levels can be obtained including zero-level or with none zero-level (NoneZero-level). Single-phase MLI inverter with 7-switches is built, simulated, and implemented practically. The system depending on modified absolute sinusoidal pulse width modulation (MASPWM) controller strategy is adopted. Simulation results clarified that MLI with NoneZero-level provides output voltage with total harmonic distortion (THD) percent less than with zero-level. The THD of the 15-level output voltage with zero-level is 3.39%, while with NoneZero-level is 3%, respectively. The system is tested at different output levels. The THD values at different output voltage levels is reduced by 12% depending on NoneZero-level state. Depending on what has been achieved, the system has been implemented practically with NoneZero-level and the THD value was 3.1%. These results prove the success of the suggested MLI circuit and MASPWM controller to obtain the required voltage level and THD.

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Design and implementation of single bit error correction linear block code system based on FPGA

Aug 4, 2019

Journal TELKOMNIKA Telecommunication, Computing, Electronics and Control

publisher TELKOMNIKA Telecommunication, Computing, Electronics and Control

DOI http://doi.org/10.12928/telkomnika.v17i4.12033

Volume Vol.17, No.4

Abstract Linear block code (LBC) is an error detection and correction code that is widely used in communication systems. In this paper a special type of LBC called Hamming code was implemented and debugged using FPGA kit with integrated software environments ISE for simulation and tests the results of the hardware system. The implemented system has the ability to correct single bit error and detect two bits error. The data segments length was considered to give high reliability to the system and make an aggregation between the speed of processing and the hardware ability to be implemented. An adaptive length of input data has been consider, up to 248 bits of information can be handled using Spartan 3E500 with 43% as a maximum slices utilization. Input/output data buses in FPGA have been customized to meet the requirements where 34% of input/output resources have been used as maximum ratio. The overall hardware design can be considerable to give an optimum hardware size for the suitable information rate.

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Scheduling lecturer system based on FPGA

Mar 14, 2018 - Mar 15, 2018

Publisher IEEE

DOI https://ieeexplore.ieee.org/document/8370955

Country Iraq

Location Wasit - Kut, Iraq

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