Publications
"Hardware Implementation of 3D-Bresenham's Algorithm Using FPGA"
Mar 4, 2013Journal Tikrit Journal of Engineering Sciences
Issue no. 2
Volume Vol.20
Traditional 3D-Bresenham's algorithm is efficient in generating lines on raster systems using only integer calculations. This algorithm is needed as a solution of hidden surface problem using depth-buffer method to calculate z value for each pixel, while calculated values of x and y are used to address frame buffer memory, z value is used to test hidden surface by saving the closest depth in depth buffer. In this paper Bresenham's algorithm for plotting 3D-lines is examined then modified to simplify hardware requirements during implementation phase. Basing on efficiency of the algorithm on the space symmetry an enhanced version of this algorithm is implemented using OpenGL. Experimental results confirm results calculated theoretically for both traditional and modified algorithms. The hardware implementation is accomplished for real time applications, and a graphic subsystem is designed using FPGA. Finally, a comparison is accomplished for Spartan3E utilization which is used to implement the hardware unit.
A Real Time Dynamic 3D Graphics Processor Using FPGA
Jul 1, 2013Journal International Journal for Research and Development in Engineering (IJRDE)
Issue Issue.1
Volume Vol.2
Complex three dimensional dynamic graphics processing is computationally very intensive process due to the trigonometric complex algebra and matrices based operations that required to be performed in real-time, so even the newest microprocessors cannot handle more complicated scenes in real time. Therefore to produce realistic rendering for the dynamic 3D graphics hardware solution is required. Since real time graphics processing requires extremely high performance, hardware solutions is used with FPGA technology to improve in performance. This paper a dynamic 3D graphics processor is designed with a transformation unit to generate an animated objects and it is implementation on FPGA by using Xilinx Spartan-3E XC3S1600E kit as a fully functional graphics rendering engine using VHDL and Xilinx's development tools. The designed graphics processor is implemented successfully on FPGA using Spartan-3EXC3S1600E and the dynamic time consumed is 7.246 μ seconds for the designed transformation unit so it is capable to transform approximately 138M vertices per second.
Robust Image Watermarking for Tamper Detection andSelf-Recovery Using SVD and RSA Methods
Jul 4, 2024Journal CENTRAL ASIAN JOURNAL OFMATHEMATICAL THEORY ANDCOMPUTER SCIENCES
Issue 3
Volume 5
To The paper proposes an Image watermarking technique for identifying and self-recovering tampered images. The system identifies tampered images by comparing the SVD values of 4X4 blocks and average pixel intensities of 2×2 blocks. In the process of SVD computation, the RGB channel images are divided into 4X4 blocks, after which a further 2X2 blocks division is executed for determination of average pixel intensity. Within the same block, tamper-detection data is entered, whereas the self-recovery data is scattered all over the image utilising inverse and RSA techniques for neighborhood block-based recovery. This method assures easy long-term self-healing. The outputs produced from testing with 15 multiple host images in varied attacks were constantly performing better with a PSNR ratio upto an average of 45 dB.